1. Field of the Invention
This invention relates to a reproduction apparatus for reproducing a disk on which, for example, digital audio data are recorded, and in which errors resulting from malfunctions of the error correction system caused by linking portions of the recording are reduced.
2. Description of the Related Art
When, for example, an audio signal is converted into a digital signal and is recorded and reproduced, it is recorded after it has been processed by error correction coding processing. Then, upon reproduction, a correctable error is corrected using the error correction coding. As the error correction coding, a cross-interleave Reed-Solomon code (CIRC) system is frequently used (as in, for example, compact disks), since it is superior in that it has a strong error correction capability and is implemented using relatively small-scale circuitry.
Since the CIRC system used for a compact disk is of the convolution type, and is not of the block-completion type, when new data are to be recorded later in a linking relationship to previously-recorded data such that the former is continuous in recorded position while being discontinuous in time from the latter, a great interleave error takes place at the linking portion between them when error correction decoding processing is performed during reproduction.
In the following, this will be described with regard to the CIRC system, using the compact disk as an example.
FIG. 1 particularly illustrates the recording processing and reproduction processing for the CIRC system in a signal recording and reproduction system for a compact disk. The two Reed-Solomon codes employed in the CIRC system are individually called C1 and C2, and upon recording, digital audio data are supplied in parallel in units of 24 bytes to the scramble circuit 1, in which scrambling of the data is performed. The data are then supplied to the C2 encoder 2, in which a (28, 24, 5) Reed-Solomon code C2 of GF(2.sup.8) is produced and a parity Q of 4-byte length is added to this. Accordingly, data of 28 bytes are obtained from the C2 encoder 2 and are supplied to an interleave circuit 3, in which interleave (rearrangement of data) processing up to a maximum interleave length of 108 frames (1 frame corresponds to 32 bytes) is performed.
Subsequently, the C1 encoder 4 generates a (32, 28, 5) Reed-Solomon code C1 of GF(2.sup.8) and adds a parity P of 4-byte length to this. Thus, data in frames of 32 bytes are obtained from the C1 encoder 4 and are supplied to the recording modulation circuit 5, in which addition of a synchronizing signal, eight-to-fourteen modulation (EFM) and some other necessary processing are performed for the data and the resulting data are converted into serial data. The serial data are recorded onto the disk 6.
Data read out from the disk 6 by means of an optical head are digitized by binary digitizing by the RF (radio frequency) amplifier 7 and are then supplied to the reproduction demodulation circuit 8. The reproduction demodulation circuit 8 performs EFM demodulation and some other necessary processing to obtain parallel data in units of one frame (32 bytes). The parallel data are supplied to an error correction decoding section 10. The error correction decoding section 10 functionally includes the C1 decoder 11, the deinterleave processing section 12, the C2 decoder 13 and the descramble processing section 14.
The Reed-Solomon code C1 allows detection and correction of a 2-byte error, and correction of a correctable error is performed by the C1 decoder 11. After such error correction by the C1 decoder 11, the deinterleave processing section 12 processes the data by deinterleave processing, that is, by rearrangement processing to re-arrange the data which have been re-arranged by the interleave processing performed during recording to restore the original arrangement of the data. Thereafter, the C2 decoder 13 performs error correction decoding processing of the data based on the Reed-Solomon code C2, using the result of the error correction decoding processing performed by the C1 decoder 11. Then, the data are rearranged back to original order of the audio data by the descramble processing section 14 to obtain an output of digital audio data.
In the reproduction system of FIG. 1, binary digitized output data of the RF amplifier 7 has the structure shown in FIG. 2A with 32 bytes=1 frame, where each byte is represented by (m.n) (m is the frame number, and n is the number of the byte in the frame).
Then, in the error correction decoding section 10, data are practically re-arranged in units of one byte as shown in FIG. 2B in a memory, and the two series C1 and C2 of the re-arranged data are processed for the detection and correction of errors.
The C1 series includes 32 bytes in the vertical column of FIG. 2B, which are data for one frame of the output signal of the RF amplifier 7, for example: data (1.1), (1.2), (1.3), . . . , (1.n), . . . , (1.31) and (1.32). The lowermost four bytes (1.29), (1.30), (1.31) and (1.32) are the parity P. As described above, the C1 series allows detection and correction of an error of 2 bytes.
Meanwhile, the C2 series includes 28 bytes taken from previously-reproduced data. One byte is taken from every four frames (except for the parity bytes P of the frame), as seen from the oblique line in FIG. 2B. For example, bytes (-103.1), (-99.3), (-95.2), . . . , (-107+4n.n), ..., (1.28) as seen from FIG. 2B, and those of the data which are actually utilized as audio data are 24 bytes in the 28 bytes, while the remaining 4 bytes are the parity Q which is used for error detection and correction.
The C2 series also allows the detection and correction of an error of 2 bytes, and if used together with the error pointer indicating the error detection for the C1 series, then error correction of up to 4 bytes is possible.
A flow chart of an example of a conventional processing routine for error detection and correction which utilizes such C1 and C2 series is shown in FIGS. 3 and 4.
Referring to FIGS. 3 and 4, calculation of the parity P is performed first for data of the C1 series of 32 bytes of one frame obtained from the RF amplifier 2 (step 101). Next, it is determined whether or not the data of the C1 series include an error or errors (step 102). If the data of the C1 series include no error, the control sequence immediately advances to step 103, where "OK", that is, a code which indicates no error, is written into a pointer (an index representative of whether the byte is or is not an error) for each of the 28 data bytes.
When it is detected at step 102 that the data of the C1 series include an error or errors, the control sequence advances to step 104, where it is determined whether or not the number of errors in the data of the C1 series is equal to or smaller than the number of correctable errors which can be corrected. If the number of errors is equal to or smaller than the correctable error number, that is, the error number equal to or smaller than 2 bytes, the control sequence advances from step 104 to step 105, where the error or errors are corrected. Thereafter, the control sequence advances to step 103, where "OK" is stored into all of the pointers for the 28 bytes.
On the other hand, when it is determined at step 104 that the number of errors detected is equal to or greater than 3 and the errors cannot be corrected, the control sequence advances to step 106, where "NG", that is, a code indicating an error, is written into the pointers for all 28 bytes.
From step 103 or step 106, the control sequence advances to step 107, shown in FIG. 4, where calculation of the parity for the C2 series is performed using the previously-reproduced data, and then to step 108, where it is determined whether or not the C2 series includes an error or errors.
If the C2 series includes no error, then the control sequence immediately advances to step 109, where "OK" is written into pointers for the 24 data bytes of the C2 series and the resulting data are outputted.
On the contrary, when it is determined at step 103 that the C2 series includes an error or errors, the control sequence advances to step 110, where it is detected whether or not the number E of errors in the C2 series is equal to or smaller than the number m of correctable errors which can be corrected (E.ltoreq.m). Since erasure correction is performed for such error or errors here, the correctable error number m is 4.
If the number E of errors in the C2 series is smaller than the correctable error number m, then the control sequence advances from step 110 to step 111, where the pointers generated by the calculation of the respective C1 series and the results of calculation of the C2 series are collated with each other. Then, it is determined at step 112 whether or not the result of the collation indicates a coincidence in the number of errors between them.
The processing at steps 111 and 112 serves as wrong correction detection means for preventing wrong correction of errors such as detecting correct data as an error and correcting the data in error.
When the result of the determination at step 112 proves coincidence, the control sequence advances to step 113, where correction of the error or errors in the C2 series is performed, and then to step 109, where a flag of "OK" is added to all of the data of the 24 bytes of the C2 series and the resulting data are outputted.
On the other hand, when the result of the determination at step 112 proves non-coincidence between the detected number of errors and the number of "NG" in the pointers of the C1 series, the control sequence advances to step 114, where another "NG" flag is added to all of the pointers of the data of the 24 bytes of the C2 series and the resulting data are outputted.
Further, when the number of errors detected by the calculation of the parity for the C2 series is greater than the correctable error number m at step 110, the control sequence advances to step 115, where it is determined whether or not the number of data bytes whose pointers indicate "NG" is greater than m. This is performed by referring to the pointers of the result of the processing of those C1 series that have bytes in the C2 series.
If it is determined at step 115 that the number of data bytes whose pointers indicate "NG" is equal to or smaller than m, since it is considered that either the error detection for the C1 series or the error detection for the C2 series is wrong, the control sequence advances to step 114, where the flag "NG" is added to all of the pointers of the data of the 24 bytes of the C2 series and the resulting data are outputted.
On the other hand, when the number of data bytes whose pointers indicate "NG" as the result of the processing of the C1 series is greater than m, it is determined that the result of calculation for the C1 series coincides with the result of calculation for the C2 series. The control sequence advances from step 115 to step 116, where the flag of "OK", or "NG" is added to each of the data bytes in accordance with the result of the processing of the C1 series, and the resulting data are outputted.
It is to be noted that, using the flag of "OK" or "NG", interpolation of data is performed for the bytes of "NG" by the technique of average value interpolation or thresholding.
The error flags outputted as the result of error detection and correction based on the C1 and C2 series as described above are divided into the following three categories:
1. No error (no error is detected from the C1 and C2 series; PA1 2. "OK" or "NG" (E&gt;m in both of the C1 and C2 series ); and PA1 3. All errors (results of processing of the C1 and C2 series do not coincide with each other).
If a system which performs error correction decoding processing based on such convolution-type signal processing performs linking recording, in which new data are recorded in a linking relationship to a previously-recorded area, then when data are rearranged in units of one byte in a memory in a manner such as that shown in FIG. 2B, the data are recorded in a condition such as that shown in FIG. 5A. In this condition, there is the problem that the area of the linking portion, in which the data are all determined to be errors, is large, as seen in FIG. 5B.
In particular, at the physical linking position, the clock signal of the previously-recorded data is not synchronized with the clock signal of the subsequently-recorded data. This forces the phase-locked loop (PLL) circuit that synchronizes the clock signal during reproduction out of its phase-locked condition. As a result of this, all data of the C1 series in a section of about 300 bytes in 5 to 10 frames following the physical linking position are determined as consecutive errors. Then, when calculation of parity for the C2 series is performed, data of C2 series up to the C2 series immediately prior to the C2 series indicated at S1 in FIG. 5B (the small circles represent data bytes included in the C2 series) correspond to the case in which one or two errors normally occur, as described above, and thus the errors in them are corrected in almost all cases, and there is no problem. Further, even if errors which cannot be corrected remain, processing appropriate to such a case can be performed, and, again, there is no problem.
However, in the case of the C2 series indicated at S2 in FIG. 5B, even if it is determined that there is no error outside the C1 error area in FIG. 5B, while the number of errors obtained by calculation of parity for the C1 series is 2, the number of errors is determined to be 3 as a result of calculation of parity of the C2 series. This is because, in addition to the two errors detected from the C1 series, one byte of the data linking recorded later is included in the C2 series. This corresponds to the third abnormal condition described above and is detected at steps 111 and 112 serving as the wrong correction detection means of FIG. 4. Consequently, all of the 24 byte data of the C2 series are determined to be errors. In short, correct data previous to and following the C1 error area, which inevitably generates errors because of the disruption of the clock signal at the linking portion, are also determined to be errors.
The condition in which all of the data bytes of the C2 series are determined to be errors continues as far as the C2 series indicated at S4 in FIG. 5B, and consequently, continuous errors are determined over about 120 frames.
In particular, if conventional error correction decoding processing, such as the routine shown in FIGS. 3 and 4, is executed at the linking portion of a linking recording, the inevitable errors over 10 frames or so are determined in error as continuous errors extending over about 120 frames. The malfunctioning of the error correction decoding results in the disadvantage that data that was originally correctly reproduced from the disk is not correctly decoded.
In a recording and reproduction system conforming to a compact disk such as, for example, a CD-MO, when linking recording is to be performed, a sufficiently large invalid data section is provided at the linking portion to prevent such a disadvantage as that described above. Consequently, when there are a large number of instances of linking recording on a disk, the utilization efficiency of the recordable area of the disk is very low.
Meanwhile, the assignee of the present invention has proposed a disk recording and reproducing apparatus in which audio data are recorded on a magneto-optical disk having a diameter smaller than that of a compact disk, for example, a diameter of 64 mm. The audio data are compressed and are intermittently recorded in recording units of a predetermined amount of compressed audio data. The compressed audio data are read out intermittently from the disk and are stored once into a buffer memory. Then, the data are read out from the buffer memory at a suitable rate and are expanded to reproduce the original audio data (refer to, for example, U.S. patent application Ser. No. 07/745,486, now U.S. Pat. No. 5,317,553).
The disk recording and reproducing apparatus can be formed in such a small size as to allow realization of a portable apparatus since it utilizes a small disk.
With the disk recording and reproducing apparatus described above, since intermittent recording is involved, linking recording is performed for every intermittent recording unit. When the recording unit for such intermittent recording and reproduction is set to 32 sectors of audio data (a sector corresponds to a block of a CD-ROM and is about 2 kbytes), there are about 2,000 linking recording portions on a disk capable of recording an audio signal for 74 minutes. Therefore, providing an area for invalid data at each linking portion would seriously impair the efficiency of use of the recording area of the disk.
Further, while it is possible to provide a user area, into which subdata are to be recorded, immediately prior to the data of each intermittent recording unit, if the area of a linking portion is made excessively small, then when a position error is caused by displacement in rotation of a disk or the like, there is a disadvantage in that data in the subdata area may not possibly be reproduced.